1. Field of the Invention
The present invention relates to a data processor executing pipeline processing, and specifically relates to a data processor executing memory indirect addressing and register indirect addressing in an address calculation stage.
2. Description of Related Art
A pipeline processing system has been employed for increasing the processing speed of the data processor.
The pipeline processing system increases throughput by dividing instruction processing and simultaneously executing a plurality of instructions in a data processor, and thereby increases the apparent speed of executing one instruction. For example, in a data processor constructed so as to execute one instruction in a pipeline of four stages of instruction decoding, operand address calculation, operand fetch and operation execution, a maximum of four instructions are executed simultaneously in the respective processing stages. On the other hand, in a data processor executing processing an instruction one by one, only after all processings of instruction decoding, operand address calculation, operand fetch and operation execution for one instruction have been completed, the next instruction processing can be executed. Accordingly, the data processor executing pipeline processing can have an instruction processing speed apparently quadruple in comparison with the data processor executing processing an instruction one by one.
To further increase the processing speed of the data processor, it is required to raise the efficiency of pipeline processing. To raise the efficiency of pipeline processing, it is required that load of each stage of pipeline is equal, each stage processes data in same clock cycle, and pipeline processing progresses one after another.
Causes of disturbing progress of continued data processing in the pipeline include jump instruction, exception, interruption, conflict between instructions in the pipeline and the like. One of the major conflicts in the pipeline is that the operand address calculation stage refers to a general-purpose register or a memory whereto the operation execution stage writes data before a writing thereof.
To correctly execute instructions following a program, the operand address calculation stage must refer to a general-purpose register or a memory after the operation execution stage has completed a writing to the general-purpose register or the memory.
FIG. 1 is a circuit block diagram explaining a conventional pipeline controlling mechanism.
In FIG. 1, numeral 41 designates an instruction decoder, which decodes an instruction, outputs a register writing reservation signal to a set input of an SR (set reset flip-flop 42 for register writing processing, and outputs a memory writing reservation signal to a set input of a SR flip-flop 43 for memory writing processing. The SR flip-flop 42 for register writing processing and the SR flip-flop 43 for memory writing processing are reset by reset signals RS1 and RS2 from an operation processing part 44, respectively.
FIG. 2 is a status view explaining changes of pipeline processing.
In FIG. 2, numeral 51 designates an instruction decoding stage, numeral 52 designates an address calculation stage, numeral 53 designates an operand fetch stage, numeral 54 designates an operation execution stage, T1 through T8 designate processing cycles, and I1 through I3 designate instructions flowing through the pipeline.
Next, description is made on a conventional pipeline controlling sequence attending on a writing to a register or a memory in reference to FIG. 1.
The instruction decoder 41 checks if an inputted instruction writes data to a register or a memory in the operation processing part 44. Subsequently, when it writes to the memory, it outputs a memory writing reservation signal to set the SR flip-flop 43 to "1". The set value of the SR flip-flop 43 is reset to "0" when processing of the instruction, which set "1" to the SR flip-flop 43, in the operation processing part 44 is completed, and thereafter the instruction processing is resumed.
Like the case of a writing to a memory, also in writing to a register, the SR flip-flop 42 is set by a register writing reservation signal, and is reset when processing of that instruction is completed in the operation processing part 44. A stage delay by such pipeline control is described in reference to FIG. 2.
For example, when the instruction I1 reserves a writing to a memory, processing of the instruction I2 stops in the processing cycle T3, and decoding processing cannot be executed until the instruction I1 writes data to the memory on the processing cycle T4. A stop signal is reset in the processing cycle T4, and the instruction I2 resumes the processing in the cycle T5. Resultingly, a delay of two cycles takes place for the instruction I2. A similar delay takes place also in the case of register writing reservation.
For this reason, a proposal of improving this problem attending on the register conflict as mentioned above has already been made, for example, as shown in the U.S. patent application Ser. No. 156,271 (based on the Japanese Patent Application No. 62-144394).
However, the conventional method has a problem that when the preceding instruction writes a value to a memory, the following instruction stops operand address calculating processing until the preceding instruction completes a writing to the memory, resulting in a remarkable reduction in the pipeline processing speed.